1. Technical Field
The embodiments described here relate to a semiconductor memory apparatus, and more specifically, to a clock driver device for a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus is configured to include a clock generation circuit, such as a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit, to generate an internal clock signal having a phase leading by a predetermined time in comparison to an external clock signal. For example, in a double data rate synchronous dynamic random access memory (DDR SRAM) device, the internal clock signal output from the clock generation circuit includes a rising clock signal and a falling clock signal, wherein the rising clock signal has a phase opposite to the falling clock signal. The rising clock signal is used to output data from the rising edge of the external clock signal in a data output buffer, and the falling clock signal is used to output data from the falling edge of the external clock signal in the data output buffer.
In order to transfer the rising clock signal and the falling clock signal, which are output from the clock generation circuit, to the data output buffer, it is necessary to drive the clock generation circuit by a driver. Accordingly, the semiconductor memory apparatus commonly include a clock driver to drive the rising clock signal and the falling clock signal. Here, the clock driver is designed to be activated when an active command signal is input and deactivated when a precharge command signal is input, such that it is operated only in an active mode.
FIG. 1 is an operational timing diagram of a conventional semiconductor memory apparatus. In FIG. 1, a rising clock signal ‘rclk’ and a falling clock signal ‘fclk’ generated from the clock generation circuit are generated to have a phase leading by a delayed amount generated while each of the rising clock signal ‘rclk’ and a falling clock signal ‘fclk’ is transferred to the data output buffer. However, a glitch in the data output buffer can occur since a high section of the rising clock signal ‘rclk’ and the falling clock signal ‘fclk’ is narrower than a low section thereof.
The clock driver generates a clock output enable signal ‘ckoen’, which is enabled when an active command signal ‘act’ is input and disabled when a precharge command signal ‘pcg’ is input, and drives the rising clock signal ‘rclk’ and the falling clock signal ‘fclk’ only in a section where the clock output enable signal ‘ckoen’ is enabled to output a rising driving clock signal ‘rdclk’ and a falling driving clock signal ‘fdclk’. However, the active command signal ‘act’ is commonly input to other semiconductor memory apparatuses in a memory module.
FIG. 2 is a schematic block diagram of a conventional semiconductor memory apparatus. In FIG. 2, clock enable signals ‘cke<1:5>’, which instruct an entry to a power-down mode, are individually input to first to fifth semiconductor memory apparatuses 2 to 6 arranged in a memory module 1, but the active command signal ‘act’ is commonly input thereto. Accordingly, a situation where the active command signal ‘act’ is input to any one semiconductor memory apparatus entering the power-down mode among the first to fifth semiconductor memory apparatuses 2 to 6 can occur. Since the clock driver is operated in response to only the active command signal ‘act’, such that the clock driver included in the semiconductor memory apparatus can be continuously activated despite the power-down mode, power consumption increases.
In the semiconductor memory apparatus, the clock driver is considerably spaced apart from the data output buffer. Accordingly, a length of a transmission line between the clock driver and the data output buffer increases. Even though the data output operation is not actually performed due to several reasons, such as the entry into the power-down mode, if the clock driver continuously supplies the rising driving clock signal and the falling driving clock signal to the data output buffer, then current consumption occurs along the transmission line with a relatively long clock signal.